1. Field of the Invention
The present invention relates to a low current consumption FIFO (First In First Out) circuit capable of implementing a FIFO function of high-speed data.
A high-speed serial transmission system according to USB 2.0 High Speed Standard (transmission rate: 480 Mb/s) or the like allows a certain error between the transmission rate of external data and the frequency rate of an internal clock signal (±500 ppm for USB 2.0). To absorb the frequency error between the two rates, a FIFO circuit is generally used. The present invention relates to the FIFO circuit that handles such high-speed data, which is simple in structure with low current consumption and high operation speed. Although the following embodiments in accordance with the present invention are explained by way of example of the USB 2.0 High Speed Standard, the application field of the FIFO circuit in accordance with present invention is not limited to the USB 2.0 standard.
2. Description of Related Art
A FIFO circuit is one of memory circuits generally used for exchanging data with different frequencies. It writes data synchronized with a clock signal A, and reads data in the same sequence as the write sequence using a clock signal B different from the clock signal A.
The following document describes a conventional example of the FIFO circuit.
Yoshitaka Toriumi, Masaharu Taharazako, and Kenji Yokomizo, “15. FIFO (synchronous bus): Chapter 2, Practical Sample Description of VHDL/Verilog-HDL of special issue, Don't Fear HDL anymore!”, Design Wave Magazine, pp. 57-59, January, 2000.
The conventional FIFO circuit has a complicated logic for detecting the full or empty state of the FIFO to prevent its underrunning and overrunning, thereby bringing about an increase in the scale and a decrease in the speed of the circuit.
In addition, it is difficult for the conventional FIFO circuit to increase its speed because the memory access causes a bottleneck by applying an SRAM or the like which is accessed by addresses to its memory array. On the other hand, constructing the memory array by registers like a flip-flop circuit will increase the current consumption, thereby presenting a problem of making it difficult to implement a low current consumption FIFO circuit.